Efficient Computer jobs

Efficient Computer is hiring a Senior Product Manager - Software to own strategy and direction for the company's developer platform, including compiler, SDK, runtime integrations, and developer experience. Responsibilities include defining product roadmap, setting priorities based on customer requirements, driving framework enablement, and establishing SDK governance. Location is San Jose, CA (on-site). This is a product management role, not software engineering.

Efficient is building ultra-low-power AI processors that enable perpetual computing on AA batteries, and this role owns ATLAS—a critical hardware regression testing and CI/CD infrastructure platform—plus serves as the primary CI/CD owner across three engineering teams. You'll develop Go services and C/C++ test programs, manage Kubernetes clusters with hardware-attached nodes, operate PostgreSQL and Redis systems, and maintain GitHub Actions pipelines while acting as the go-to person for CI/CD reliability and developer experience across the organization. The ideal candidate brings 5+ years in infrastructure/DevOps/test engineering with strong hands-on experience in Go, C/C++, Python, Kubernetes, Docker, and GitHub Actions, plus demonstrated expertise operating CI/CD systems for multiple teams and familiarity with embedded hardware bring-up and performance profiling. Efficient offers competitive salary ($160K–$210K depending on experience and location), meaningful equity, 401K match, and comprehensive benefits including paid parental leave and flexibility. A standout requirement is the combination of full-stack infrastructure depth (cloud CI/CD, self-hosted runners, package management) with embedded systems credibility—this is a rare blend that directly impacts product development velocity across a hardware-focused organization.

Efficient is seeking a Lead RTL Design Engineer in Austin, San Jose, or Pittsburgh to own microarchitecture definition and RTL implementation for an energy-efficient processor SoC that runs AI/ML on AA batteries for years. The role spans dataflow execution fabric, memory subsystem, on-chip interconnect, low-power logic, and peripheral IP integration—working from architecture spec through synthesis-ready RTL while collaborating cross-functionally with architects, DV, physical design, and firmware teams. Required qualifications include 8+ years of RTL design with tape-out ownership on dataflow-based designs, on-chip networks, memory subsystems, or peripheral integration for processor or accelerator SoCs, plus deep proficiency in (qualifications text cuts off). This is a senior position at a newly formed hardware org where you'll shape product direction, mentor engineers, drive PPA metrics, and support silicon bring-up for an industry-leading power-efficient chip. The company's core differentiation is 100x lower energy consumption than state-of-the-art ultra-low-power processors, enabling perpetual edge AI/ML deployment.