System Validation Senior Staff Engineer
YokneamSenior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM )
Santa Clara, CASenior Staff Design Verification Engineer – Memory Sub-System (DDR/LPDDR/HBM )
Santa Clara, CADigital IC Design Junior Engineer
Cordoba, ArgentinaSenior Staff Design Verification Engineer – PCIE/CXL Sub-System
Irvine, CA · Santa Clara, CAPhotonics Chip Lead
Santa Clara, CA · US-CADirector of Silicon Design for MEM/PCIE COE
Santa Clara, CASenior Staff Design Engineer - PCIE/CXL Subsystem COE
Santa Clara, CASenior Staff Design Verification Engineer – Memory Sub-System
Santa Clara, CASenior Staff Design Engineer - PCIE/CXL Subsystem COE
Irvine, CASenior Staff Design Verification Engineer – PCIE/CXL Sub-System
Irvine, CA · Santa Clara, CASenior Staff Design Verification Engineer
Toronto, CanadaSenior Staff Engineer, ASIC/VLSI Synthesis and Design
Irvine, CA · US-CAEmbedded System Intern for Pre-Silicon Validation
Cordoba, ArgentinaEngineering Program Manager / Project Manager
US-CASenior Principal Engineer- HBM PHY
BangaloreStaff Quality & Reliability Engineering Engineer
Santa Clara, CADigital Design Verification Intern
Cordoba, ArgentinaSenior Principal Analog Lead – HBM PHY
BangaloreSenior Analog Layout Engineer
Singapore
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