Physical Design Flow & Methodology Engineer

Physical Design Flow & Methodology EngineerOn-siteHardware EngineeringFull timePune, Maharashtra, IndiaShare this job DescriptionQuadric delivers its GPNPU as soft IP — RTL and implementation collateral — enabling customers to integrate our processor into their own SoCs across a range of process nodes and foundries. You will drive PPA optimization across IP configurations, build the scalable reference flows customers use to evaluate and integrate our IP, and provide hands-on implementation support to customers working toward their tapeouts.Responsibilities PPA Optimization & AnalysisDrive PPA analysis and optimization for Quadric GPNPU soft IP across process nodes and hardware configurations — timing, area, leakage, and dynamic powerApply low-power techniques (clock gating, multi-Vt, operand isolation) and synthesis/P&R knobs to hit frequency and area targetsCharacterize the IP design space across configurations and build PPA models that support customer evaluations and pre-sales engagementsPartner with RTL and architecture teams early to quantify tradeoffs and influence design decisions before they become costly to reverse Reference Flow DevelopmentBuild and maintain a scalable RTL-to-GDS reference flow for Quadric soft IP that customers can use to evaluate, integrate, and close PPA in their own SoC environmentEnsure the flow is portable across supported process nodes with clear BKMs, SDC templates, floorplan scripts, and integration guidelinesDevelop TCL and Python automation — and leverage AI coding tools such as Claude — to accelerate flow development, reduce manual effort, and improve repeatabilityQualify EDA tool updates and benchmark QoR impact before rolling into the reference flow Customer Integration & Tapeout SupportAct as the primary PD contact for customers integrating Quadric soft IP, guiding them from evaluation through their SoC tapeoutHelp customers adapt the reference flow to their process node, foundry PDK, and internal design environmentTriage and resolve customer-reported implementation issues — timing, congestion, power, or flow failures — working with internal teams to deliver fixes or updated collateralSupport FAE and business development with PPA feasibility studies for new customer engagements Collaboration & DocumentationWork with architecture, RTL, and software teams to ensure IP deliverables meet customer-facing PPA targetsDocument methodologies, BKMs, and optimization learnings; maintain process node bring-up guidelines to support IP portabilityRequirements Education & ExperienceBS/MS in Electrical Engineering, Computer Engineering, or related field7+ years of ASIC or processor IP physical design experience focused on PPA optimization and flow development across advanced nodes Technical SkillsProficiency with industry-standard physical design tools from Synopsys or Cadence (synthesis, place-and-route, and timing analysis)Experience with advanced FinFET process nodes (16nm and below); multi-node experience preferredStrong TCL scripting and Python automation skillsSolid understanding of synthesis and P&R levers for PPA — timing paths, cell selection, congestion, and power intentHands-on experience with low-power design techniques and MCMM timing analysisComfort using AI tools (e.g., Claude, Copilot) to accelerate script development, automate repetitive EDA tasks, and improve workflow productivityUnderstanding of DFT concepts (scan, ICG bypass) and their physical design implications Nice to HaveExperience delivering soft IP to external customers or supporting SoC integrators through tapeoutBackground in AI accelerator, NPU, or DSP processor IP implementationExposure to metrics-driven QoR tracking and large-scale synthesis run managementApply for this jobThis website uses cookies to improve user’s experience, personalise ads and analyse traffic. You can accept all cookies, decline all optional cookies, or manage your cookie settings. To learn more, view our cookies policy.Cookies settingsAccept...