About The Role
As our team grows Cerebras is looking for a world class physical design engineer. We are looking for a strong learner who can learn how we do PD and integration of our wafer scale design.
As a member of our tight knit physical design team, you will perform a variety of physical design tasks such as synthesis, place and route, timing and block closure / sign off. You will be involved in all aspects of physical design and implementation. You will work closely with the RTL team and with full-chip integration of these blocks.
Skills and Qualifications
7+ years of physical design/verification experience.
Strong experience in block/subsystem timing closure.
Strong ability to learn and grow with the team.
Strong knowledge of block level and full-chip physical verification methodology.
Expert at optimizing for the best power/performance and area.
Experience with the complete physical design flow. Knowledge of Synopsys tool suite is a plus.
Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
Expert with IR/EM analysis and resolution.
Good understanding of full chip floor-planning and integration.
Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.
Demonstrated ability to work with RTL teams to optimize for physical design.
Ability to take on a leadership role after ramping up on wafer scale design