Technologist, RFIC Design Engineer

Google Chrome Microsoft Edge Apple Safari Mozilla Firefox Technologist, RFIC Design EngineerFull-timeJob Type (exemption status): Exempt position - Please see related compensation & benefits details belowSalary Range: 170,600.00-227,400.00Business Function: ASIC DevelopmentWork Location: San Jose Great Oaks Headquarters--LOC_WDT_USCA23Location (Secondary): Irvine Office--LOC_WDT_USCA01Company DescriptionWD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in. We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide. This isn’t theoretical work. It’s real systems, at real scale, people solving some of the hardest challenges in technology today. We’re looking for people who want to build, solve, and operate at that level. Join us and let’s shape the future of data.Job DescriptionESSENTIAL DUTIES AND RESPONSIBILITIES:Designer will be responsible for the design of high performance RF and analog circuit blocks.Responsibilities include transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification, preparation of test plan for the testing team, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation.Job responsibilities require ability to communicate at all levels and with cross functional groups.Candidate must have good verbal and written communications skills and demonstrated track record of circuit innovation, must be a team player, be adaptable, and accept constructive feedback.QualificationsREQUIRED:Must have hands-on design and development experience in RF and analog integrated circuitMust have experience in at least one preferably multiple area of full CMOS circuit design and development in:Baseband amplifiers, low noise RF amplifiers, wide bandwidth amplifiersMixers, up-converters, down-convertersHigh speed drivers and receivers, CDR circuits, equalizersPower amplifiersMust have experience in 40nm and below CMOS technologyMust have a demonstrable track record of successful design releases and mass productionMust have thorough knowledge of industry standard EDA tools (Cadence, Mentor, Siemens, Ansys etc.)Experience with RF and high performance analog block layout such as LNA, mixer, analog to digital converters, references, digital to analog converters etc.Experience with floor planning, block level routing and top level chip routingKnowledge of high performance analog layout considerations such as matching, EM-IR and SOA and mitigation techniquesExperience working with distributed design teams a plusMust possess strong written and verbal communication skillsBS, MS or PhD with relevant experienceAdditional InformationWD is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected...