Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

Skip to main contentOur CompanyOur BusinessSearch for JobsJoin Talent NetworkFAQsProfileEnglishSign InSingle PositionView All JobsNext-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design EngineerSan Diego, California, United States of AmericaApply NowAdd to Job CartFind out how well you match with this jobUpload your resumeJob descriptionCompany and benefitsJob ID3094285Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:Job DescriptionNext Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory subsystems.. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products.The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory subsystems into QCT products. You will develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.Qualifications Bachelor's  or Masters degree in Science, Engineering, or related field.5+ years ASIC design, RTL coding, front-end digital design experience3+ years Hardware Architecture experiencePreferred Qualifications 3-10 years of ASIC design (RTL coding) PreferredExposure to RTL Design Verification flows is a plus3+ years of direct Hardware Architecture experienceBachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design Master's degree preferredExperience with the following:LPDDR  memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processorsExposure to HBM memory type designsOn-chip tightly coupled SRAM & L3 cache controller architecture/designExperience with x86 or ARM CPU/bus architecturesOrdering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specificationEducation Requirements Required: Bachelor's, Computer Engineering and/or Electrical EngineeringPreferred: Master's, Computer Engineering and/or Electrical EngineeringMinimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. ORMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. ORPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide...