ASIC Engineer, Physical Design

Skip to main content ASIC Engineer, Physical Design Meta Sunnyvale, CA Apply Join or sign in to find your next job Join to apply for the ASIC Engineer, Physical Design role at Meta Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. ASIC Engineer, Physical Design Meta Sunnyvale, CA 6 days ago Be among the first 25 applicants See who Meta has hired for this role Apply Join or sign in to find your next job Join to apply for the ASIC Engineer, Physical Design role at Meta Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. Save Report this job Meta provided pay range This range is provided by Meta. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $178,000.00/yr - $250,000.00/yr Meta is building custom silicon to power the next generation of infrastructure and consumer hardware, including data center accelerators and wearable devices. The Physical Design team is responsible for translating RTL into manufacturable, high-performance silicon by owning the full physical implementation flow from floorplanning through signoff. In this role, you will drive physical design strategy for complex ASIC blocks, define implementation methodologies, and partner closely with architecture, design, and verification teams to deliver chips that meet aggressive power, performance, and area targets at advanced process nodes.ASIC Engineer, Physical Design Responsibilities:Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff across advanced process nodesDefine and drive physical design methodology, flow development, and best practices across the physical design organizationPerform and own timing closure, including static timing analysis, timing constraint authoring, and multi-corner multi-mode signoffDrive power integrity analysis and optimization, including IR drop, electromigration, and dynamic power reduction techniquesCollaborate with RTL design and architecture teams to provide physical design feedback on microarchitecture decisions, floorplan feasibility, and design-for-manufacturabilityPartner with custom layout and circuit design teams to integrate analog and mixed-signal blocks into the digital physical implementation flowDevelop and maintain physical design scripts, automation flows, and...