Senior Staff Engineer Chip Package Board - CoDesign Flow and Methodology (f/m/div)

Skip to main contentSystem update notice: From 22 July to 3 August, application processing will be delayed due to a system update.Job SearchMy ActivityProfileCareersFAQsBenefitsJoin Talent NetworkSign InEnglishSingle Position#WeAreInView All JobsSenior Staff Engineer Chip Package Board - CoDesign Flow and Methodology (f/m/div)Villach (Austria)Apply NowSave JobFind out how well your profile matches this jobUpload your resumeJob descriptionBenefits and company informationJob IdHRC1712314Job FamilyResearch & DevelopmentType of EmploymentFull timeDuration of EmploymentPermanentJoin asProfessional (incl. Management Positions)#WeAreIn for jobs that impact everyone's life. Join the thinkers, builders, and problem-solvers behind tomorrow’s technology. As a Senior Staff Engineer Chip Package Board - CoDesign Flow and Methodology on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?Your RoleKey responsibilities in your new roleDefine and drive the technical roadmap for Chip-Package-Board (CPB) design methodologies, flows, tools, and digital engineering capabilities. Partner closely with Business Lines, Design Centers, and engineering communities to understand current and future product requirements, technology trends, and business challengesTranslate Business Line needs into methodology enhancements, design-flow improvements, simulation capabilities, automation concepts, and EDA roadmap requirements. Act as the technical bridge between Business Lines, methodology teams, software teams, IT organizations, and EDA vendorsDrive continuous improvement of CPB methodologies and engineering workflows to accelerate design convergence, improve design quality, and increase first-pass success. Establish scalable, reusable, and sustainable methodology solutions, standards, and governance models across the CPB ecosystemIdentify and shape future capabilities required for advanced packaging, heterogeneous integration, System-in-Package (SiP), 3D design methodologies, multi-domain simulation, and AI-assisted engineering workflows. Evaluate and influence EDA vendor technologies and industry trends to ensure alignment with Infineon's future business needs Lead AI, automation, data, and digitalization initiatives that deliver measurable engineering and business value. Drive the evolution towards an integrated, data-driven, AI-enabled, and highly automated CPB co-design environment Provide technical leadership, consulting, training, and enablement for global user communities and stakeholders. Build strong partnerships across engineering functions and drive adoption of methodology and digital engineering solutionsYour ProfileQualifications and skills to help you succeedDegree in Electrical Engineering, Microelectronics, Physics, Computer Engineering, or a related technical discipline, with a minimum of 8 years of experience in semiconductor development, design methodologies, EDA environments, package development, design automation, simulation, or related engineering fieldsStrong understanding of semiconductor product development, including chip, package, board, simulation, and system-level interactions. Ability to understand Business Line challenges, technology roadmaps, and future product requirements, and translate them into methodology strategies, flow enhancements, and technical development roadmapsProven experience in defining, optimizing, and deploying engineering methodologies and design flows. Strong analytical and strategic thinking skills, with the ability to identify future requirements and drive technology evolution beyond day-to-day operational supportExperience working with EDA technologies and vendors (e.g., Cadence, Synopsys, Keysight, Comsol). Good understanding of digitalization, automation, AI-enabled engineering workflows, and data-driven engineering concepts....