SOC Design Verification Engineer, Staff– Pre-Si/Post-Si Verification

Skip to main contentOur CompanyOur BusinessSearch for JobsJoin Talent NetworkFAQsProfileEnglishSign InSingle PositionView All JobsSOC Design Verification Engineer, Staff– Pre-Si/Post-Si VerificationTijuana, Baja California, MexicoApply NowAdd to Job CartFind out how well you match with this jobUpload your resumeJob descriptionCompany and benefitsJob ID3094006Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:We are seeking motivated Engineer and Senior Engineer candidates to join our Pre-Silicon and Post-Silicon SoC Verification team. In this role, you will verify next-generation SoCs that power Mobile, AI, high-performance computing, and cloud infrastructure products. The position spans pre-silicon simulation, emulation, acceleration, and post-silicon bring-up/validation activities, with responsibilities aligned to the candidate’s experience level.Engineer-level candidates will contribute to verification execution, debug, test development, and coverage closure under technical guidance. Senior Engineer-level candidates will additionally lead feature-level verification planning, drive complex debugs across pre-silicon and post-silicon environments, mentor junior engineers, and influence methodology improvements across projects.Key Responsibilities – Pre-Si and Post-Si Verification:· Develop and execute verification plans for SoC, subsystem, and IP-level features across pre-silicon and post-silicon phases.· Build, enhance, and maintain SystemVerilog/UVM, C/C++, processor-based, emulation, and acceleration verification environments.· Create directed, constrained-random, stress, performance, power, and system-level test scenarios to validate architecture and real-use-case behavior.· Develop assertions, functional coverage models, checkers, scoreboards, and signoff metrics for verification closure.· Debug RTL, testbench, emulation, firmware, ATE/vector, and silicon bring-up issues using logs, waveforms, traces, and hardware debug data.· Support post-silicon validation, silicon characterization, ATE pattern debug, failure triage, and correlation between simulation, emulation, and silicon results.· Drive coverage closure, regression health, bug tracking, and verification signoff using functional, code, assertion, and scenario coverage metrics.· Participate in architecture, micro-architecture, design, validation, and test-plan reviews to ensure verification and bring-up requirements are captured early.· Verify complex SoC features including multi-core CPU systems, cache coherency and interconnect fabrics, DDR/HBM memory subsystems, PCIe/CXL/Ethernet/high-speed interfaces, security, performance, and power-management features.· For Engineer level: execute assigned verification tasks, develop tests and checkers, debug failures, maintain regressions, and contribute to coverage and bring-up activities.· For Senior Engineer level: own feature/subsystem verification from plan to closure, lead debug across teams, mentor engineers, identify schedule and quality risks, and drive methodology/automation improvements.· Contribute to reusable verification components, scripting automation, AI-assisted verification workflows, and continuous improvement of pre-silicon and post-silicon validation processes.Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. ORMaster's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. ORPhD in Science, Engineering, or related field.Minimum Qualifications· Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science, or related field.· Engineer: typically 2+ years of relevant design verification, validation, or SoC debug experience.· Sr. Engineer: typically 4+ years...