HBM PHY System Architect (San Diego, US)

Skip to main contentOur CompanyOur BusinessSearch for JobsJoin Talent NetworkFAQsProfileEnglishSign InWelcome to an enhanced Qualcomm Careers platform! We’ve reimagined our site to streamline your experience as you explore opportunities and invent the future with Qualcomm. Get started by creating a profile using sign in, setting your preferences, and managing your Qualcomm job search—all in one place. Note: Your past applications will be available when you sign in using the same email address you previously used to apply.Single PositionView All JobsHBM PHY System Architect (San Diego, US)San Diego, California, United States of AmericaApply NowAdd to Job CartFind out how well you match with this jobUpload your resumeJob descriptionCompany and benefitsJob ID3093643Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:QCT mixed-signal IP design team is looking for skilled system architects to design high-speed, high-performance, and low-power HBM Phys. You’ll help with system definition, architecture, and end-end design cycle - starting from early ideas all the way to final chip production and validation.Responsibilities:Own the HBM PHY architecture and system definition, driving end-to-end solutions that meet performance, power, area, and reliability targets.Develop and manage system timing budgets across on-die, and off-chip interfaces, ensuring robust operation across all conditions.Lead cross-functional architectural trade-offs and execution, working closely with SoC, memory, package, and validation teams.Deliver best-in-class HBM PHY solutions through technical leadership, innovation, and alignment with product roadmap requirements.Required for this Role:5+ years of experience in HBM PHY architecture and design for high-performance memory interfaces.Strong understanding of JEDEC memory standards (HBM, LPDDR, DDR) and their application to PHY architecture and design.Expertise in link budgeting, timing closure, margin analysis, and PHY training methodologies for high-speed interfaces.Proven ability to drive technical discussions and collaborate effectively across cross-functional and globally distributed teams.Preferred Qualifications:Familiarity with signal integrity (SI), power integrity (PI), package effects, and power delivery networks for high-speed memory systems.Knowledge of advanced process technologies, mixed-signal design principles, and high-speed interface implementation.Understanding of design-for-yield, manufacturability, and production challenges associated with high-speed memory links.Proficiency in Unix/Linux environments and scripting languages such as Perl, TCL, or Python for automation and analysis.KeywordsHBM, DDR, DRAM, PHY, high-speed interface, signal integrity, power integrity.Educational RequirementsRequired: Bachelor's, Electrical EngineeringPreferred: Master's, Electrical EngineeringMinimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. ORMaster's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. ORPhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that...