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๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฎ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฒ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฎ๐ฌ-๐ฒ๐ฌ ๐๐ฃ๐)
Experience: 5+ yrs
Location: Bengaluru, Karnataka, India, India
Job Type: Full-time
We are seeking an experiencedย Static Timing Analysis (STA) Engineerย to drive timing closure and sign-off activities for advanced SoC designs across cutting-edge semiconductor technology nodes. This role is ideal for professionals with deep expertise inย Static Timing Analysis, timing optimization, and sign-off methodologies, who thrive in a collaborative VLSI development environment.
As an STA Engineer, you will be responsible for performing comprehensive timing analysis, driving timing convergence, implementing Engineering Change Orders (ECOs), and working closely with Physical Design, Synthesis, and Clock Tree Synthesis (CTS) teams to ensure successful tape-outs. You will play a critical role in delivering high-performance, reliable, and timing-clean semiconductor designs.
Requirements
Key Responsibilities
- Perform block-level and full-chipย Static Timing Analysis (STA)ย for complex, high-performance SoC designs.
- Drive timing closure throughout the design lifecycle, including pre-layout and post-layout stages.
- Analyze and resolve setup, hold, recovery, removal, maximum transition, maximum capacitance, and fanout violations.
- Executeย MCMM (Multi-Corner Multi-Mode)ย timing analysis and optimization to ensure robust design performance.
- Collaborate closely with Physical Design, Synthesis, CTS, Routing, and ECO teams to achieve timing convergence.
- Generate, review, and interpret timing reports while identifying and resolving critical timing paths.
- Implement and validate ECOs to improve timing performance and support design optimization.
- Support timing sign-off activities, including signal integrity (SI) analysis and low-power timing verification.
- Contribute to successful tape-outs by ensuring compliance with timing, quality, and design requirements.
- Develop automation scripts and improve STA workflows to enhance productivity and design efficiency.
What Makes You a Great Fit
- 5+ years of hands-on experience inย Static Timing Analysis (STA)ย for advanced SoC designs.
- Strong expertise inย Synopsys PrimeTimeย and timing sign-off methodologies.
- Proven experience withย MCMM timing analysis, timing closure, and sign-off flows.
- Deep understanding of timing constraints (SDC), clock architecture, timing exceptions, and optimization techniques.
- Hands-on experience withย PrimeTime SIย for signal integrity analysis.
- Strong knowledge of Physical Design processes, including Floorplanning, Placement, CTS, Routing, and ECO implementation.
- Experience working on advanced technology nodes such asย 5nm, 7nm, 12nm, 16nm, or 28nm.
- Proficiency inย TCLย and Shell scripting for automation and workflow optimization.
- Strong debugging, analytical, and problem-solving skills with attention to detail.
- Exposure to tools such asย Synopsys ICC2ย orย Cadence Innovus, along with knowledge of OCV, AOCV, POCV, LVF, CPPR, Crosstalk, IR Drop, EM analysis, UPF/CPF, or high-speed interface timing, will be an added advantage.