Job Details:

Job Description: 

The Role and Impact As a DFT Design Engineer, you will play a pivotal role in shaping the future of Intel's products by ensuring excellence in Design for Test (DFT) strategies. This role is instrumental in delivering high-quality, reliable, and testable System-on-Chip (SoC) designs that meet the demands of modern computing. You will collaborate across architecture, design, verification, and manufacturing teams to implement advanced DFT techniques, enabling optimal silicon performance, faster production ramp-up, and outstanding quality for Intel's cutting-edge products. By joining our team, you will directly contribute to Intel's mission to design and deliver leading semiconductor technologies that power the world's digital transformation. Key Responsibilities - Develop logic designs and register transfer level (RTL) code for DFT features, including SCAN, MBIST, and BSCAN. - Provide DFT timing closure support and deliver test content for manufacturing. - Collaborate in defining architecture and microarchitecture features of blocks, subsystems, and SoC designs under DFT. - Create high-volume manufacturing (HVM) content to support rapid bring-up and ramp on automatic test equipment (ATE). - Write and optimize RTL and structural code for DFT integration while balancing power, performance, area, timing, test coverage, and design integrity objectives. - Review verification plans and drive the verification of DFT designs to ensure compliance with architecture specifications and standards. - Implement corrective measures for failing RTL tests to ensure proper design functionality. - Integrate DFT blocks into functional IP and SoC designs and support SoC customers with high-quality integration. - Partner with post-silicon and manufacturing teams to validate DFT features on silicon, support debug requirements, and document improvements for future designs. - Drive high test coverage through structural and IP-specific tests to meet product quality and defect-per-million (DPM) objectives.

Qualifications:

Minimum Qualifications - Bachelor's or BS degree in Electrical Engineering, Computer Engineering, or a related field. - 0-1+ years of experience with a Bachelor's degree or 0 years with a Master's degree. - Proficiency in RTL design languages such as Verilog and SystemVerilog. - Knowledge of DFT concepts, tools, and techniques, including SCAN, MBIST, and BSCAN. - Experience with electronic design automation (EDA) tools and methodologies. - Familiarity with digital design fundamentals and logic design optimization. Preferred Qualifications - Strong problem-solving and debugging skills, with attention to detail and disciplined execution. - Experience with lint tools and test automation workflows. - Effective collaboration and communication skills to work across multidisciplinary teams. - Enthusiasm for learning new concepts and contributing to innovative solutions. We are looking for passionate individuals ready to innovate and make an impact. Apply today to be part of Intel's journey toward creating the future of technology.

          

Job Type:

College Grad

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.