ASIC Engineer, Physical Design

**Summary:** Meta's silicon engineering team is building custom infrastructure silicon to power the compute demands of AI, data center, and next-generation hardware platforms. As an ASIC Engineer focused on Physical Design, you will drive the physical implementation of custom ASICs from floorplanning through tapeout, working across a full-custom silicon design flow. In this role, you will collaborate closely with RTL design, verification, and package engineering teams to deliver high-performance, power-efficient silicon that underpins Meta's infrastructure at scale. **Required Skills:** ASIC Engineer, Physical Design Responsibilities: 1. Execute physical design tasks including floorplanning, placement, clock tree synthesis, routing, and timing closure for custom ASIC designs 2. Perform static timing analysis and work to resolve setup and hold violations across design corners and operating conditions 3. Collaborate with RTL and logic design engineers to ensure design-for-physical-implementation guidelines are met early in the design cycle 4. Develop and refine physical design scripts and methodologies to improve automation, quality of results, and turnaround time 5. Conduct power analysis and implement power optimization strategies including clock gating, multi-voltage domain partitioning, and IR drop mitigation 6. Run and interpret physical verification signoff checks including DRC, LVS, and ERC to ensure design compliance with foundry rules 7. Partner with package and board engineers to define bump maps, power delivery networks, and IO ring constraints 8. Contribute to the development and documentation of physical design flows, best practices, and reusable block-level methodologies 9. Analyze and resolve congestion, signal integrity, and electromigration issues across hierarchical design blocks **Minimum Qualifications:** Minimum Qualifications: 10. 2+ years of experience in ASIC physical design, including hands-on work with placement, clock tree synthesis, routing, and timing closure 11. Experience performing static timing analysis using tools such as Synopsys PrimeTime or equivalent 12. Experience with physical verification flows including DRC and LVS signoff using Calibre or equivalent tools 13. Experience scripting in Tcl, Python, or shell to automate physical design tasks and flows **Preferred Qualifications:** Preferred Qualifications: 14. Experience with advanced process nodes (7nm or below) and associated design rule complexity 15. Familiarity with low-power design techniques including multi-voltage domains, power gating, and dynamic voltage and frequency scaling 16. Experience with hierarchical physical design methodologies for large, multi-million gate ASIC designs 17. Exposure to custom data center or infrastructure silicon design from block-level implementation through tapeout **Public Compensation:** $114,000/year to $172,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.