AI - UVM Verification Engineer

Role responsibilities

The UVM Verification Engineer will develop and maintain SystemVerilog/UVM testbenches to verify complex RTL designs. Responsibilities include creating test plans, executing tests, debugging failures, and collaborating with various teams to ensure functional correctness.

Requirements

Candidates should have strong RTL Design and Functional Verification skills, along with experience in SystemVerilog and UVM. A Bachelor’s or Master’s degree in a related field is required, and familiarity with scripting languages is beneficial.

Key skills

AI, UVM, SystemVerilog, Debugging, Validation, Digital Design, EDA Tools, Scripting, ASIC Design, SoC Design, Quality Compliance, Test Plans, Simulation, Mentoring, Collaboration, Automation

Keywords

AI, UVM, Verification, Engineer, SystemVerilog, Testbenches, RTL, Debugging, Simulation, EDA Tools, Scripting, ASIC, SoC, Quality Compliance, Automation, Mentoring, Collaboration