ASIC Engineer, Architecture

**Summary:** Meta's Silicon Engineering organization is building custom silicon solutions that power the infrastructure underpinning Meta's AI and data center workloads at scale. As an ASIC Engineer specializing in architecture, performance and modeling, you will define and drive the architectural performance analysis, pre-silicon modeling, and microarchitectural exploration of custom ASICs designed for Meta's infrastructure. In this role, you will establish functional and performance modeling methodologies and long-term silicon roadmap strategy, as well as develop and analyze workloads, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale. **Required Skills:** ASIC Engineer, Architecture Responsibilities: 1. Drive microarchitectural exploration and trade-off analysis across compute, memory subsystem, interconnect, and I/O domains to inform silicon architecture decisions 2. Define and own the performance modeling strategy for custom infrastructure ASICs, including development of cycle-accurate and transaction-level simulation environments 3. Develop and maintain C++ models of AI chip IPs and subsystems for architecture exploration, performance analysis, and software development 4. Develop low-level workloads and kernels for machine learning training and inference applications 5. Establish performance analysis methodologies, benchmarking frameworks, and bottleneck identification techniques across the full ASIC pipeline 6. Collaborate with architecture, RTL design, and physical design teams to translate performance requirements into implementable microarchitectural specifications 7. Partner with software and systems teams to co-optimize workload scheduling, firmware, and driver behavior against silicon performance characteristics 8. Lead cross-functional technical reviews and communicate performance modeling results and architectural recommendations to engineering leadership 9. Define long-term performance modeling infrastructure roadmaps, including tooling, automation, and simulation platform investments 10. Mentor other engineers on performance modeling techniques, simulation methodology, and microarchitectural analysis best practices 11. Identify and resolve performance gaps between modeled and measured silicon behavior through structured root-cause analysis and model calibration **Minimum Qualifications:** Minimum Qualifications: 12. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 13. 6+ years of experience in ASIC design, silicon engineering, or a related technical field 14. Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools 15. 5+ years of experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs 16. Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon 17. Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems including processors, memory subsystems, or high-speed interconnects 18. Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams 19. Experience with assembly programming languages, and compiler technologies **Preferred Qualifications:** Preferred Qualifications: 20. Experience with AI numerics, data types, math functions, and precision/accuracy analysis 21. Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies 22. Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization 23. Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs 24. Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows 25. Experience writing and optimizing compute/collective kernels in CUDA or equivalent GPU programming frameworks 26. Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis **Public Compensation:** $146,000/year to $209,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.