Senior Hardware Engineer - Micro-Architect

Senior Hardware Engineer - Micro-ArchitectOn-siteHardware EngineeringFull timeBurlingame, California, United StatesShare this job DescriptionQuadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and hardware is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart-sensor systems to high-performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators in the industry today that can only accelerate a portion of a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code.Role:This is a rare opportunity to get in on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle.Our preference is for a candidate located in the California Bay Area who can regularly collaborate from our Burlingame office. From time to time, the team and company gather for onsite meetings and offsite events. These in-person moments are an important part of how we build relationships, collaborate effectively, and align on priorities, and participation is expected for all team members.Contribute to the definition of the processor architecture by understanding its applicationsOwn microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilogOwn Power, Performance & Area (PPA) optimizationContribute to timing closure through full product cycle (front end, back-end, tapeout)RequirementsBS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end designProficiency in SystemC, SystemVerilog, or VerilogStrong background in computer architectureKnowledge of design techniques for low power digital designKnowledge of VCS & Verilog/C Co-SimExperience in data-parallel hardware design for high-performance computingExperience in FPGA design is a plusExperience in logic synthesis and performance modelingNice to haves:Familiarity with automotive safety (ASIL) standards Expected Outcomes in 12 months:Independently own a major design block and improve PPA Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stackPackage design for customer releases and incorporate customer feedbackBenefitsAt Quadric, we value Integrity, Humility, and Happiness. What we expect from one another is simple and clear: Initiative, Collaboration, and Completion. We are a collaborative team focused on building something extraordinary in the edge computing space. Competitive salary and meaningful equityMedical, dental, and vision plan options starting on day one401(k) retirement planFlexible paid time off (unlimited, non-accrual) to support work-life balanceWhen working in-office, enjoy company-provided lunches and a stocked kitchenConvenient office location within walking distance of the Caltrain stationSupport for commuting, including monthly parking or Caltrain passesDowntown Burlingame office location, close to shops, cafes, and local amenitiesA politics-free, highly collaborative environment where talented people can do their best work and make an immediate impactThe opportunity to build long-term career relationships in a company that values strong personal connections alongside professional excellenceThe base salary range for this position is $110,000 to $270,000. This range reflects the full span of levels and geographies at which Quadric hires for this role. The actual base salary offered will depend on a number of factors, including the specific level of the role, years and depth of relevant experience, technical skills and competencies, the criticality of the role to the business, internal equity, and work location. In addition to base salary, this role is eligible for equity and a...