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๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ฏ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ฐ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ฏ๐ฌ-๐ฐ๐ฌ ๐๐ฃ๐)
Experience: 6+ yrs
Location: Bengaluru
Job Type: Full-time
We are seeking an experiencedย SoC Verification Engineerย to join a high-performing VLSI engineering team responsible for verifying complex System-on-Chip (SoC) designs. This role is ideal for professionals with strong expertise in SoC verification methodologies, SystemVerilog, UVM, and processor-based verification who are passionate about delivering high-quality silicon.
As a SoC Verification Engineer, you will play a key role in planning, developing, and executing comprehensive verification strategies for complex SoC and subsystem designs. Working closely with Design, IP, and Physical Design teams, you will build scalable verification environments, debug functional issues, and drive verification closure to ensure robust, high-performance silicon implementations.
Requirements
Key Responsibilities
- Develop and execute comprehensive SoC and subsystem verification plans aligned with project requirements.
- Build, enhance, and maintain reusable UVM-based verification environments and testbench components.
- Perform functional verification of complex SoC designs using SystemVerilog, UVM, and industry-standard verification methodologies.
- Verify IP integration and ensure seamless interaction between multiple SoC components.
- Debug simulation failures, perform root cause analysis, and collaborate with design teams to resolve issues efficiently.
- Verify AMBA-based interfaces including AXI, AHB, and APB protocols.
- Drive functional and code coverage closure while ensuring verification quality and completeness.
- Develop and utilize SystemVerilog Assertions (SVA) to improve verification effectiveness.
- Collaborate with Design, Physical Design, and cross-functional engineering teams throughout the verification lifecycle.
- Support verification sign-off by ensuring all quality, performance, and coverage goals are successfully achieved.
What Makes You a Great Fit
- 6+ years of experience in SoC or Subsystem Verification within VLSI design environments.
- Strong hands-on expertise inย SystemVerilogย andย Universal Verification Methodology (UVM).
- Proven experience building reusable UVM verification environments and SoC-level testbenches.
- Solid understanding of processor-based SoC verification, preferably with ARM-based architectures.
- Strong knowledge ofย AMBA protocols, includingย AXI, AHB, and APB.
- Experience using industry-standard simulators such asย VCS, Questa, or Xceliumย for verification and debugging.
- Expertise in functional coverage, code coverage, and verification closure methodologies.
- Hands-on experience with SystemVerilog Assertions (SVA) and advanced debugging techniques.
- Exposure to low-power verification (UPF/CPF), emulation, FPGA validation, or scripting with Python, Shell, or Perl is an added advantage.
- Excellent analytical, debugging, communication, and collaboration skills with a strong commitment to delivering first-pass silicon quality.