Senior Silicon Digital Design Engineer, Core IP

Senior Silicon Digital Design Engineer, Core IP _corporate_fare_ Google _place_ Bengaluru, Karnataka, India **Mid** Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. **Minimum qualifications:** + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. + 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. + Experience with ASIC design methodologies for clock domain checks and reset checks. **Preferred qualifications:** + Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science. + Experience implementing machine learning accelerators or camera ISP image processing IP or other multimedia IPs such as display or video codec. + Proficient in scripting languages, C/C++ programming and software design skills. + Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture. **About the job** Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. **Responsibilities** + Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration. + Define and develop RTL implementations that meet power, performance and area goals. + Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks. + Participate in synthesis, timing/power closure and FPGA/silicon bring-up. + Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning. Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google'sApplicant and Candidate Privacy Policy (./privacy-policy) . Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See alsoGoogle's EEO Policy (https://www.google.com/about/careers/applications/eeo/) ,Know your rights: workplace discrimination is illegal (https://careers.google.com/jobs/dist/legal/EEOC\_KnowYourRights\_10\_20.pdf) ,Belonging at Google (https://about.google/belonging/) , andHow we hire (https://careers.google.com/how-we-hire/) . If you have a need that requires accommodation, please let us know by completing ourAccommodations for Applicants form (https://goo.gl/forms/aBt6Pu71i1kzpLHe2) . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.