ASIC Engineer, Design Verification

Skip to main content ASIC Engineer, Design Verification Meta Sunnyvale, CA Apply Join or sign in to find your next job Join to apply for the ASIC Engineer, Design Verification role at Meta Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. ASIC Engineer, Design Verification Meta Sunnyvale, CA 1 week ago 68 applicants See who Meta has hired for this role Apply Join or sign in to find your next job Join to apply for the ASIC Engineer, Design Verification role at Meta Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. Save Report this job Meta provided pay range This range is provided by Meta. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more. Base pay range $114,000.00/yr - $172,000.00/yr Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing advanced ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will be using other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.ASIC Engineer, Design Verification Responsibilities:Define and implement block/IP/System on Chip (SoC) verification plans, build verification test benches to enable block/IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamCollaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality through defined verification metrics and coverage goalsMinimum Qualifications:Currently has, or is in the...