ASIC DV Engineer, Simulation Acceleration and Hybrid Verification

**Summary:** Meta is hiring an ASIC Verification Engineer with background in Simulation Acceleration using Emulation and Hybrid Platforms within the Infrastructure organization. We are looking for individuals with experience in Simulation Acceleration and Emulation to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with experienced engineers across the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be responsible for the verification closure of a sub-system or SoC from test-planning, Hybrid test bench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC DV Engineer, Simulation Acceleration and Hybrid Verification Responsibilities: 1. Propose, implement and promote the Simulation Acceleration and Hybrid Verification Methodology to be used across the group, both at the Cluster and at the SoC level 2. Work with Architecture and Design teams to come up with functional, use case and performance test plan for the DUT 3. Define Verification scope, create environment, testplans and close use case scenarios and performance using targeted tests at Cluster and SoC level 4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team 5. Develop and drive continuous Hybrid Verification improvements using the latest methodologies, tools and technologies from the industry 6. Build reusable/scalable environments for Hybrid Verification. Evaluate and recommend solutions for Hybrid Verification and Simulation Acceleration 7. Provide training for internal teams and mentoring of engineers related to Hybrid Verification Methodology **Minimum Qualifications:** Minimum Qualifications: 8. 6+ years of relevant experience 9. Hands-on experience in Verilog, SystemVerilog, UVM, C/C++, Python based verification 10. Experience of working with Zebu, Palladium, Veloce HW platforms 11. Experience in Cluster and SoC level verification using Hybrid Simulation and Emulation based methodologies 12. Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments 13. Experience in architecting and implementing Hybrid Verification infrastructure and executing verification cycle **Preferred Qualifications:** Preferred Qualifications: 14. Experience with revision control systems like Mercurial(Hg), Git or SVN 15. Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification 16. Experience working across and building relationships with cross-functional design, model and emulation teams 17. Experience with verification of ARM/RISC-V based sub-systems or SoCs 18. Experience in verification of Data-center applications like Video, AI/ML and Networking designs or integration verification of high-speed interfaces like Ethernet PCIe, DDR, HBM 19. Experience with simulators and waveform debugging tools 20. Experience in performance verification of complex compute blocks like CPU, GPU or HW Accelerators, Ethernet, PCIe, DDR, HBM etc 21. Experience in development of Simulation Acceleration and Hybrid verification environments from scratch 22. Track record of 'first-pass success' in ASIC development **Industry:** Internet