GPU Physical Design Methodology Engineer (Lead/Staff)

Skip to main contentOur CompanyOur BusinessSearch for JobsJoin Talent NetworkFAQsProfileEnglishSign InSingle PositionView All JobsGPU Physical Design Methodology Engineer (Lead/Staff)Hyderabad, Telangāna, IndiaApply NowAdd to Job CartFind out how well you match with this jobUpload your resumeJob descriptionCompany and benefitsJob ID3092586Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.Minimum Qualifications:• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.As a member of the Graphics team, the successful applicant will help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams. The successful candidate will possess basic understanding of RTL design and ASIC design flow from RTL to GDS such as synthesis, static timing analysis, formal verification, physical design, ECO generation and verification. They will collaborate with multiple functional teams including design, technology, power, implementation, sign-off and post-silicon to drive PPA improvements into GPU cores.Knowledge and experience in the following is a definite advantage:· Implementation and delivery of GPU cores from RTL to GDSII· Semi-custom design flow and methodology development· Identifying areas for flow and process improvements· Verilog and System-Verilog languages· RTL synthesis using physically aware tools· Design constraint management for power, timing, clocking, interfaces· Formal Verification for RTL-netlist and netlist-netlist checks· Clock Tree Analysis and Optimization· ECO methods for functional and timing fixes· Managing design goals and tradeoffs in power, performance, and areaPreferred Qualifications:At-least 5-7 years of experience developing methodologies for PPA improvementBasic understanding of digital design and RTL development Hands on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower,PrimeTime and Prime ClosureScript writing experience in UNIX shell, Python, Perl and/or TCLExcellent interpersonal and analytical skills as well as ability to work independentlyHighly motivated, excellent team spirit, obsession with deliverable quality and customer orientedApplicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals...