Senior Performance Architect

Senior Performance ArchitectHybridR&DFull timeBurlingame, California, United StatesShare this job DescriptionQuadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and hardware is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart-sensor systems to high-performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators in the industry today that can only accelerate a portion of a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code.As a Senior Performance Architect, you will be the critical link between software and hardware, responsible for understanding how code executes on Quadric's architecture and identifying opportunities for optimization. You will analyze workloads from high-level C++ and Python down through generated assembly to pinpoint performance bottlenecks. This is a hands-on role: beyond analysis, you will prototype solutions yourself - whether that means writing optimized code, modifying compiler passes, or building proof-of-concept implementations to validate proposed fixes before handing off to the appropriate team for productization.This role requires regular work from the Quadric office in Burlingame, CA, a minimum of 2–3 days per week, with some weeks requiring more days onsite based on business needs. Candidates must be able to commute to the office. ResponsibilitiesAnalyze application performance across the full stack: C++/Python source, compiler output, assembly, and hardware executionIdentify and localize performance bottlenecks to specific code regions, assembly sequences, or architectural limitationsImplement proof-of-concept fixes and optimizations to validate proposed solutions before broader rolloutDevelop and maintain profiling infrastructure, benchmarks, and performance regression testsCollaborate with compiler engineers to improve code generation and optimization passesWork with hardware architects to identify microarchitectural improvements and validate performance modelsCreate performance models that predict workload behavior and guide optimization prioritiesDocument findings and communicate performance insights to both technical and non-technical stakeholdersSupport customer engagements by analyzing their workloads and recommending optimizationsRequirementsBS/MS in Computer Science, Computer Engineering, or Electrical Engineering with 5+ years of performance analysis experienceStrong proficiency in C++ and Python; ability to read, reason about, and write optimized code at the assembly levelHands-on mentality: comfortable implementing proof-of-concept solutions, not just identifying problemsDeep understanding of computer architecture: pipelines, caches, memory hierarchies, SIMD/vector executionExperience with profiling tools (perf, VTune, custom trace analysis) and performance debugging methodologiesAbility to trace performance issues from application behavior down to microarchitectural root causesStrong analytical and problem-solving skills with attention to detailExcellent communication skills; ability to explain complex performance issues to diverse audiencesExperience working cross-functionally with compiler, runtime, and hardware teamsNice to HaveExperience with ML/AI workloads and frameworks (PyTorch, TensorFlow, ONNX)Background in compiler development or code generationExperience with GPU, DSP, or custom accelerator architecturesFamiliarity with cycle-accurate simulation and performance modeling toolsExpected Outcomes in First 12 MonthsEstablish systematic performance analysis methodology and tooling for Quadric's software stackIdentify and drive resolution of top performance bottlenecks in key customer workloadsBuild performance models that accurately predict workload behavior within 10-15% of actual measurementsBecome the go-to...