ASIC Engineer, Design

Meta
Bengaluru, IndiaPosted Jul 20, 2026
Skip to main content ASIC Engineer, Design Meta Bengaluru, Karnataka, India Apply Join or sign in to find your next job Join to apply for the ASIC Engineer, Design role at Meta Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. ASIC Engineer, Design Meta Bengaluru, Karnataka, India 1 week ago 189 applicants See who Meta has hired for this role Apply Join or sign in to find your next job Join to apply for the ASIC Engineer, Design role at Meta Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. Save Report this job The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing and data-centre networking with superior capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.ASIC Engineer, Design Responsibilities:Architecture explorationMicro-architecture development and RTL codingSoft and hard IP identification, selection and integrationCollaboration with verification and emulation teams in test plan development and debugCollaboration with implementation team to close the design on synthesis, timing and powerMinimum Qualifications:Bachelor's degree in Electronics and Communication, Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience6+ years of silicon development experience with experience of first-pass success in ASIC (Application-Specific Integrated Circuit) DevelopmentExperience in one of these skills: Micro-architecture and RTL development for complex control/data path and networking IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology developmentExperience with RTL coding using Verilog or System VerilogLint, CDC (Clock Domain Crossing), Synthesis and Power OptimizationPreferred Qualifications:Experience in data path...

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