ASIC Engineer, Implementation [Low-Power Design]

**Summary:** Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads. As an engineer focused on implementation, you may drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will work on power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications. You will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets aggressive PPA targets for Meta's next-generation infrastructure platforms. **Required Skills:** ASIC Engineer, Implementation [Low-Power Design] Responsibilities: 1. Define the power specification at system and module level for Idle, TDP, Typical use cases 2. Develop power modeling infrastructure in Python/C++ 3. Work with or develop architectural simulators in order to model performance and power 4. Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout 5. Apply knowledge of ASIC design processes, including leakage and dynamic power, to evaluate the impact of environment and manufacturing process on power 6. Understand system level concepts and optimize design for low-power 7. Evaluation and Implementation of low-power design techniques at different levels of abstraction 8. Collaborate with RTL designers to identify and resolve timing, area, and power issues early in the design cycle 9. Participate in design reviews and provide implementation feedback to influence upstream architectural and microarchitectural decisions 10. Power characterization on silicon: idle, TDP, use case power 11. debug power issues on silicon 12. Partner with vendors to drive low-power requirements for SoC interfaces such as LPDDR, PCIe, etc. Partner with EDA tool vendors to select and deploy the appropriate power estimation tools 13. Collaborate with internal HW/SW Co-design, Architecture, Design, DV, and Emulation teams for power flows, optimization and estimation **Minimum Qualifications:** Minimum Qualifications: 14. Bachelor's degree in Computer Engineering, Computer Science or Electrical Engineering and/or equivalent practical experience 15. 2+ years of experience with modeling and design with C++ or Python and/or an equivalent high level language 16. Experience with industry-standard EDA tools for synthesis and physical implementation (Synopsys Design Compiler, Cadence Genus, Innovus, or ICC-2) 17. Experience with scripting languages such as Tcl, Python, or Perl for flow automation and data analysis **Preferred Qualifications:** Preferred Qualifications: 18. Experience with RTL design using SystemVerilog or other HDL 19. Experience with formal verification or equivalence checking as part of an RTL-to-GDS flow 20. Architecting systems for various design scales (IP blocks, SOC, multi-chip systems) with an understanding of the tradeoffs between performance and power 21. Experience with post-silicon bringup, debugging, and identifying issues across emulator, RTL, and other abstraction levels 22. Familiarity with low-power implementation techniques such as clock gating, multi-voltage domains, and power gating 23. Background in data center or AI accelerator ASIC development 24. Knowledge of front-end and back-end ASIC tools 25. Experience with architectural performance and power models at SoC and system levels 26. Experience managing multiple design releases and working with cross-functional teams to support and debug power issues 27. Ability to communicate clearly with cross-functional internal teams and with vendors **Industry:** Internet