Principal Silicon Engineer

Principal Silicon Engineer | Microsoft Careers Skip to main content Microsoft Careers Careers Careers Search Search jobs Sign in Single PositionView All JobsPrincipal Silicon EngineerIndia, Multiple Locations, Multiple LocationsApply nowAdd to cartFind out how well you match with this jobUpload your resumeJob descriptionCompany and benefitsJob number200044509Date postedJul 22, 2026Work site3 days / week in-officeTravelLess than 25%ProfessionHardware EngineeringDisciplineSilicon EngineeringRole typeIndividual ContributorEmployment typeFull-TimeOverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives We’re seeking a Full-chip Integration experience professionals with solid understanding of C4/package interfaces, chip finishing, and RDL & power delivery. As part of our DPU silicon team, you’ll take on the challenge of driving our fullchip integration execution from early design exploration to signoff.  You’ll work across teams to define, develop, and drive all aspects of power & signal planning, RDL optimization, and packaging interface.  We’re working on some of the most exciting silicon projects in Microsoft, and you will help us drive our vision.ResponsibilitiesTake ownership and responsibility for our fullchip/package integrationTake an active role in early-phase design planning with die size planning, floorplanning, C4/microbump development, and RDL insertion & optimizationDevelop, enhance, and maintain full-chip integration methodologies; collaborate with vendors and partners to align workflows with industry practices, address tool-related issues, and improve the reliability and efficiency of full-chip finishing and integration processes.Define & drive to integration milestones across project phases; manage interaction and integration with package team & vendors to ensure continuity of entire system designManage multiple power domains & islands, ensuring correctness and robustness of the designEnsure a convergent integration process and drive package closure through all phases including final signoff for tapeoutWork across teams to identify and resolve power delivery issues, integration issues, etc; provide guidance for floorplan adjustments to address power integrity issues and continuity of the package and board designQualificationsRequired qualifications:Bachelor’s degree in computer engineering, electrical engineering, or related field7+ years of physical design experience with focus on C4 integration & chip finishingExperience with ASIC design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime) & Physical Verification tools (e.g., Calibre)Preferred qualifications:10+ years of hands-on physical design experience with focus on C4/RDL integration, chip finishing, and signoffDeep expertise in power planning, C4/microbump deployment and...