Security IP RTL Design Verification Staff Engineer

## Company: Qualcomm India Private Limited ## Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Job Area Engineering - IP Design Verification Location: Bangalore Educational Requirements Bachelor/Master's Degree in Electronics & Communication / Micro Electronics / Electrical Engineering / Computer Engineering Job Description Ownership of Security IP verification test bench and associated collaterals for next generation System-on-chip (SoC) designs across mobile, automotive, edge AI, server and other product categories. Security IPs include cryptographic engines, Root of Trust, secure boot, key management, access control, secure enclaves, random number generators and other security-critical hardware blocks. The role requires strong SystemVerilog/UVM expertise, deep debug ownership and practical understanding of hardware security verification, including functional correctness, security robustness, coverage closure and full-chip integration validation. Job responsibilities include • Ownership of Security IP DV test bench and associated collaterals including checkers, trackers, monitors, scoreboards, assertions, covergroups and functional coverage models. • Develop verification plans and test cases to cover design feature set, security use cases, threat-model requirements, negative scenarios and integration requirements. • Lead end-to-end verification of hardware security IPs and subsystems using SystemVerilog/UVM, constrained-random verification, directed testing and regression-based closure methodology. • Verify cryptographic engines and security blocks including AES, SHA-2/3, ECC, RSA, TRNG, secure boot, key management, access control, lifecycle-state controlled logic and random number generators. • Create and execute security-specific test scenarios including privilege violation checks, key access misuse, debug lockdown validation, fault-injection style scenarios and RTL-level robustness tests. • Develop and debug assertions, functional coverage, security coverage and protocol coverage for security-critical properties and interface behavior. • Work closely with system architects, RTL design, emulation, firmware, software and physical design teams on failure debug, feature interpretation, coverage closure and integration issues. • Debug regression signatures, identify root cause, drive bug fixes and improve test bench efficiency through automation and methodology improvements. • Develop and deploy scripts/tools for validation, coverage analysis, formal checks, regression triage and productivity improvement. • Support formal verification, security property checking, gate-level simulation, full-chip integration verification and post-silicon validation of security features. • Debug and root cause post-silicon issues in...