Senior/Staff Design for Test Engineer

Skip to main content Senior/Staff Design for Test Engineer OLIX Bristol, England, United Kingdom Apply Join or sign in to find your next job Join to apply for the Senior/Staff Design for Test Engineer role at OLIX Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. Senior/Staff Design for Test Engineer OLIX Bristol, England, United Kingdom 2 months ago Be among the first 25 applicants See who OLIX has hired for this role Apply Join or sign in to find your next job Join to apply for the Senior/Staff Design for Test Engineer role at OLIX Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. Save Report this job About OLIXAI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.The RoleWe are seeking highly skilled and motivated Senior/Staff DFT (Design for Test) Engineers with a strong focus on high-performance digital design to take end-to-end ownership of robust, testable silicon, from early test strategy definition to verified DFT implementation, pattern generation, and silicon bring-up. You will join a multidisciplinary group creating next-generation accelerators where digital, optical, and mixed-signal domains intersect. The ideal candidate will have extensive experience in the DFT of large-scale, high-volume ASICs and a passion for developing reliable, high-coverage test architectures that drive breakthrough AI hardwareResponsibilitiesArchitect, own, and implement the comprehensive Design-for-Test (DFT) strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution.Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria.Partner with the test engineering team to develop, validate, and optimize ATE-compatible...