Synthesis-DFT Stitch CAD Engineer

## Company: Qualcomm Technologies, Inc. ## Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of gate-level synthesis and DFT stitch solutions for the Snapdragon chips powering billions of mobile devices. The position requires Synthesis, DFT , Place and Route exposure and CAD development skills to define and develop implementation tools and methodologies for PPA, shortening design cycle time, in close collaboration with Snapdragon Design and Implementation teams. Qualcomm is using leading edge internal and EDA technologies in the Implementation domain, including pioneering in genAI/ML, and developing good-by-construction automation and PPA recipes for the most complex designs of the industry in terms of multi-voltage and Fmax-area-power goals. This role’s responsibilities will include: * Participating in the development of Qualcomm DFT stitch flow and methods, leveraging both Synopsys and Cadence solutions and tools. * Improving the SoC Synthesis and DFT Stitch methodologies for diverse Mobile, Compute, AI, IoT Snapdragon chips. * Enabling new features from EDA tools or/and internal tools for Synthesis, DFT Stitch checks. * Development and support of methodology to handle complex multi-voltage crossings on DFT paths * Support Snapdragon design teams on CAD solutions, analyze their requests, and address their requests through ticket queues. * Interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirement. * Setting up, augmenting, and maintaining a regression of complex DFT Stitch and Synthesis testcases. * Innovating with design/tool/flow techniques for area reduction, dynamic power reduction and turn-around time, leading to participation to patents. Preferred Qualifications: • Bachelor of Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field. • 5-10 years of experience in VLSI CAD, preferably Synthesis, DFT and P&R • 5-10 years of experience with scripting tools and programming languages: Python and TCL preferred. Principal Duties and Responsibilities: • Participate in Synthesis and DFT Stitch flows enablement for foundry advanced process nodes. • Lead the EDA Vendors’ roadmap on DFT stitch techniques, in collaboration with Snapdragon DFT and Implementation teams and DFT CAD team. • Participate along with Qualcomm talented AI team to R&D initiatives driving differentiation in terms of die area reduction, dynamic power, performance and turn-around time. • Deep dive on Implementation issues, such as cell legalization issues, congestion hotspots, DFT stitch failures etc. • Interface and drive EDA vendor Application Engineers on the resolution of block convergence problems faced by the Snapdragon design teams. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable...