Doctoral Thesis - Automated Layout Synthesis for Scalable Quantum Computing Cryogenic Circuit Design Automation (f/m/div)

#WeAreIn to create tiny chips and big careers. Curiosity drives progress. Will you drive it with us? As a PhD at Infineon, you'll collaborate with passionate minds, shape innovations that power tomorrow's world, and build a career where your expertise truly makes a difference. Are you in? Your Role As an industrial doctorate at Infineon, you will pursue a doctoral degree at a University and gain professional experience simultaneously - an ideal start for your career. Advance your research with us and profit from our vast network of doctoral candidates and the expertise of a university. Mentorship is handled by both professors and dedicated Infineon employees. The research is carried out in cooperation with the University of Technical University of Munich (TUM) and under the supervision of Prof. Dr. Robert Wille. We offer a doctoral research position focused on next‑generation automatic placement and routing for quantum processing units. You will develop constraint‑driven algorithms that co‑optimize electromagnetic performance, thermal budgets, and manufacturability, and integrate them into end‑to‑end design flows combining C++ core engines with Cadence Virtuoso, SKILL/PCells, and Python automation. The methodology will be validated by building automatic physical‑design generators for analog cryogenic multiplexer arrays. Ideal candidates have strong software engineering skills and experience developing EDA algorithms/tools. Familiarity with analog IC or cryogenic circuit design is a strong plus. Key responsibilities in your new role * Digital Circuit Design: Develop parametric generators and constraint-driven layout templates for cryogenic multiplexer topologies; automatically size and place analog switches on the IC to produce DRC- and LVS-clean results * Cryogenic Circuit Simulation: Integrate cryogenic device models and effects; perform operating-, process-, temperature-, and mismatch-aware circuit sizing (Monte Carlo); build simulation test benches and early design-space exploration flows * Array-Level Design: Build array-level generators for scalable MUX matrices with calibration/trimming hooks if needed, parasitic models, and package-aware parasitic elements * Global Routing Algorithm Implementation: Research and implement hierarchical, congestion-aware global routing algorithms with multi-objective cost functions and manufacturing-rule/keep-out abstractions for advanced interposer substrates * Detailed Routing and Optimization: Develop grid-based detailed routing with ground stitching, via planning, and manufacturability (DFM) checks; target million-net scalability through partitioning, parallelization, and acceleration (including distributed and GPU-ready algorithms if necessary) * Benchmarking and Evaluation: Establish evaluation metrics and benchmarks for both research tracks (generator runtime, area, power, parasitic effects, routability, wirelength, R-C, DRC/DFM violations, runtime/memory scaling) * Research Publication and Dissemination: Publish at premier EDA and quantum-engineering venues (DAC, DATE, ICCAD, ASP-DAC, SMACD, IEEE TCAD, IEEE TQE, ACM TODAES) * International Collaboration and Teamwork: Communicate and collaborate with our international analog design automation team and European CHAMP-ION partners to guarantee the success of all the above activities The learnings out of the thesis will lead to: * Deep proficiency in EM‑ and thermal‑aware microwave/cryogenic layout (controlled impedance, interposers/TSVs, thermal budgeting) * Novel multi‑objective placement and routing algorithms backed by robust, scalable solvers * Production‑quality C++/Python EDA tools integrated with existing analog IC design flows * Automated layout generators deployed to fabricate cryogenic circuit demonstrators * High‑impact research outputs (peer‑reviewed publications, research collaborations, and, where appropriate, open‑source artifacts/IP) Your Profile Qualifications and skills to help you...