Senior / Staff SoC DRAM System Engineer

## Company: Qualcomm Semiconductor Limited ## Job Area: Engineering Group, Engineering Group > Software Applications Engineering General Summary: GENERAL SUMMARY: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm DRAM system Engineer, you will design and develop DRAM system software solutions for Qualcomm IE-IOT SoC platforms, spanning Linux and RTOS environments, enabling high-performance, low-power, and real-time DRAM system experiences in heterogeneous edge computing environments. Your work will support a broad range of applications, including surveillance, smart devices, retail systems, robotics, and edge AI in physical world systems, bridging deep technical knowledge with hands-on engineering execution to deliver robust, market-ready products. Qualcomm DRAM system Engineers collaborate with cross-functional teams to assess and advance the application of company products that meet and exceed customer needs. PRINCIPAL DUTIES AND RESPONSIBILITIES: * Design, develop, and evaluate DRAM system solutions for Qualcomm IE-IOT SoC platforms, including DRAM controller, PHY, timing, calibration, and memory subsystem integration across Linux and RTOS environments. * Lead DRAM bring-up, initialization, tuning, and validation on new SoC and hardware platforms to ensure stable boot, reliable runtime operation, and production readiness. * Configure and optimize memory controller and PHY settings to meet JEDEC requirements, platform power targets, bandwidth goals, latency constraints, and system-level performance objectives. * Collaborate with SoC architecture, hardware, PCB, firmware, bootloader, kernel, validation, and DRAM vendor teams to integrate and debug memory subsystem behavior on Qualcomm IE-IOT SoC-based systems. * Perform DRAM characterization, stress testing, margin analysis, retention testing, and signal/power integrity correlation to identify stability risks and improve operating margins. * Analyze and resolve system-level memory issues across boot-up, suspend/resume, low-power modes, and runtime workloads, including failures related to timing, calibration, data corruption, bandwidth, and power state transitions. * Develop and maintain diagnostic tools, automated validation flows, test patterns, and debug procedures to improve DRAM reliability, coverage, and engineering efficiency. * Conduct detailed design reviews, validation reviews, failure analysis, and technical documentation to ensure DRAM system implementation meets performance, power, reliability, compliance, and cost requirements. * Prepare and present technical findings, design tradeoffs, validation status, and issue-resolution plans to cross-functional stakeholders and project leadership. * Participate in defining assignment objectives, planning validation activities, coordinating schedules, and driving DRAM-related deliverables to closure with minimal supervision. REQUIRED COMPETENCIES: (All competencies are required upon entry) * Demonstrates strong knowledge of DRAM subsystem architecture, including LPDDR3/LPDDR4/LPDDR5 operation, DRAM controller behavior, PHY interface, timing parameters, training, and calibration flows. * Able to lead DRAM bring-up, initialization, configuration, tuning, and validation on new SoC and hardware platforms from early silicon through production readiness. * Experienced in configuring memory controller and PHY registers to satisfy JEDEC specifications, board-level constraints, power requirements, bandwidth targets, and system-level performance goals. * Capable of performing DRAM characterization, stress testing, margin sweeps, retention validation, read/write window analysis, and failure reproduction to assess memory stability and operating margins. * Skilled in analyzing and resolving system-level DRAM issues across boot-up,...