ASIC Senior Verification Engineer

Skip to main content ASIC Senior Verification Engineer Retym, Inc Austin, TX Apply Join or sign in to find your next job Join to apply for the ASIC Senior Verification Engineer role at Retym, Inc Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. ASIC Senior Verification Engineer Retym, Inc Austin, TX 3 weeks ago Be among the first 25 applicants See who Retym, Inc has hired for this role Apply Join or sign in to find your next job Join to apply for the ASIC Senior Verification Engineer role at Retym, Inc Email or phone Password Show Forgot password? Sign in Sign in with Email or New to LinkedIn? Join now By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy. Save Report this job For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.Requirements:Key responsibilities:Ownership of block\cluster verification end to end from scratch.Lead efforts of test bench architecture, Vplan definition and functional coverage.Work closely with the design, architecture, algo teams and other stakeholders.Support other team members and mentor less experienced engineers.Requirements10+ years of experience – a mustPerformed at last 2 or more full block/system verification cycles.In depth knowledge in VLSI verification flow, languages and concepts.Experience in data path or data protocols, specifically Ethernet - preferredVerification using one of the known methodologies (eRM, UVM).ResponsibilitiesPlan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.Build verification environments using SystemVerilog and UVM.Identify and write all types of coverage measures for corner-cases.Debug the functionality with design engineers.Perform coverage collection and follow the metrices to close the full functionality. Show more Show less Seniority level Not Applicable Employment type Full-time Job function Quality Assurance Industries Semiconductor Manufacturing Referrals increase your chances of interviewing at Retym, Inc by 2x See who you know Get notified about new Senior Validation Engineer jobs in Austin, TX. Sign...