ASIC NPI Support Engineer

## Company: Qualcomm China ## Job Area: Engineering Group, Engineering Group > Hardware Applications Engineering General Summary: Job Overview We are looking for a senior ASIC NPI (New Product Introduction) Support Engineer with rich end-to-end chip delivery experience. This role will be responsible for providing full-cycle technical support for customer ASIC projects from physical implementation, tapeout, wafer fabrication, packaging to silicon bring-up. You will resolve cross-stage technical risks, coordinate with foundry, packaging house and design teams, ensure first-pass silicon success, and support mass production ramp-up for new chips. Key Responsibilities 1\. Lead technical support throughout the entire ASIC NPI lifecycle, including backend physical design review, DFM check, tapeout preparation, foundry handoff, wafer manufacturing tracking, package design collaboration and post-silicon validation support. 2\. Conduct pre-tapeout reviews on floorplan, P&R results, power grid, physical verification (DRC/LVS/ERC), antenna check, and DFM violations to eliminate manufacturability risks before tapeout. 3\. Troubleshoot critical issues encountered during tapeout release, mask making, wafer processing and packaging, and work closely with foundry process engineers to analyze yield-limiting factors. 4\. Support customer silicon bring-up, correlate post-silicon test failures with layout and process problems, carry out root cause analysis and propose revision solutions for re-spin. 5\. Establish NPI checklists, design for manufacturability rules and tapeout standard operating procedures; continuously optimize flow to improve first-pass silicon success rate. 6\. Collect customer feedback on NPI challenges, coordinate internal backend, PDK, IP and process teams to resolve escalated technical bottlenecks. 7\. Organize technical workshops, compile case studies of silicon failure and yield issues, and provide proactive technical guidance for key customer projects. 8\. Track project milestones, manage multiple concurrent NPI projects, and ensure on-time tapeout and smooth product ramp to mass production. Required Qualifications 1\. Bachelor’s degree or above in Microelectronics, Electrical Engineering, Integrated Circuit Design or related majors. 2\. At least 8 years of working experience covering ASIC physical design, tapeout and NPI silicon validation. Hands-on experience with silicon bring-up, characterization, yield ramp, production readiness and customer issue resolution. 3\. Solid experience with full backend flow: floorplan, placement, CTS, routing, timing closure, power integrity and physical signoff with EDA tools including ICC2, Innovus, PrimeTime, StarRC and Calibre. 4\. In-depth knowledge of DFM, multi-patterning, antenna effect, EM/IR signoff, and physical verification closure prior to tapeout. 5\. Familiar with foundry PDK release flow, mask data preparation (MDP), GDS release requirements, and semiconductor wafer & packaging processes. 6\. Proven experience in post-silicon failure analysis, layout-process correlation and chip re-spin root cause investigation. 7\. Strong problem-solving capability to handle cross-domain issues spanning design, layout, process and testing. 8\. Fluent written and spoken English for global customer communication and cross-fab technical coordination. 9. Strict attention to detail, excellent project coordination skills and ability to manage high-pressure tapeout schedules. Preferred Qualifications 1\. Experience supporting advanced process nodes (FinFET 7nm/5nm or mature nodes 28nm/14nm) NPI projects. 2\. Hands-on experience in foundry customer engineering, tapeout service or design service NPI roles. 3\. Proficiency in Tcl/Python scripting to automate pre-tapeout checking and data analysis. 4\. Familiarity with packaging layout, bump design, and 3D IC integration knowledge. 5\. Experience leading multi-project NPI tasks and improving first silicon...