AIML enhanced Design/Verification Methodology Engineer

Skip to main content Saved jobs(0) - AIML enhanced Design/Verification Methodology Engineer DescriptionAIML enhanced Design/Verification Methodology Engineer  This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.Who We Are:Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.Job Description:   We are seeking a Design/Verification Engineer with exposure to AIML methodologies to join our team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs using AIML enhanced methodologies. You will architect, build, and maintain UVM-based testbench environments, drive coverage-driven verification closure, and collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout. This is a high-impact position for someone who thrives on solving intricate design/verification challenges using AIML methodologies. Key Responsibilities Use both “classical” and Generative-AI methodologies to architect, develop, and maintain agents, skills, and other AI based infra-structures. The ideal person will have balanced knowledge of chip design and AIML methodologies to contribute meaningfully to the creation of architecture, design, verification, and physical design assets. These includes but not limited to:   Creating UVM-based testbench environments from ground up or enhance the existing ones. Creating verification plans with clear coverage goals and closure criteria. Performing root cause analysis of failures and work with design teams to drive resolution. Automating generation of RTL from spec.  Evaluation of industry tools.  Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent). 1 - 5 years of hands-on Design/Verification experience in an ASIC or SoC environment. Deep familiarity with AIML concepts and workflows — including awareness of agentic workflows, APIs, model selection, etc. Strong proficiency in SystemVerilog for verification (classes, constraints, functional coverage, assertions/SVA). Solid understanding of digital design fundamentals (RTL, timing, synthesis constraints). Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Proven ability to develop and drive verification plans to closure. Effective communication and collaboration skills in cross-functional team settings. ​Preferred Qualifications Master's or Ph.D. in Electrical Engineering or Computer Science. Academic or professional class projects or coursework in networking, communication protocols (e.g., Ethernet, PCIe, USB, AMBA/AXI, SPI, I2C, UART), or related areas. Experience verifying high-speed serial interfaces or protocol-level IP blocks. Familiarity with formal verification tools and techniques (e.g., JasperGold, VC Formal). Experience with emulation and FPGA prototyping platforms (e.g., Palladium, Protium, Veloce). Knowledge of scripting languages (Python, Perl, TCL) for automation of verification workflows and regression infrastructure. Experience with power-aware verification (UPF/CPF) or mixed-signal verification. Contributions to verification methodology development...