Principal Engineer – RV (EM/IR)

## Company: Qualcomm India Private Limited ## Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. We are looking for an experienced Principal Engineer – RV (EM/IR) to lead power integrity and reliability signoff activities for advanced-node SoC designs. In this role, you will drive IR drop and electromigration (EM) analysis, define signoff methodologies, and collaborate with cross-functional teams to achieve robust and reliable silicon implementation. The ideal candidate should possess deep expertise in power integrity analysis, a strong understanding of advanced-node challenges, and proven experience in leading signoff closure for complex chip designs. What You’ll Do * Lead full-chip and block-level IR drop and electromigration (EM) analysis for advanced-node SoC designs * Drive power integrity signoff closure by identifying, debugging, and resolving IR/EM violations * Collaborate with Physical Design, Power, Package, and Foundry teams to optimize power delivery networks * Define and improve EM/IR methodologies, automation flows, and signoff strategies * Perform static and dynamic IR analysis across multiple operating conditions and scenarios * Analyze power grid robustness, current density, and thermal impacts to ensure design reliability * Support tapeout activities and ensure high-quality signoff delivery within project timelines What We’re Looking For * Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline * 10+ years of experience in IR/EM analysis, power integrity, or Physical Design signoff * Strong understanding of power integrity concepts including static/dynamic IR drop, EM analysis, and power grid optimization * Hands-on experience with industry-standard tools such as Cadence Voltus, Ansys RedHawk, or equivalent * Good understanding of Physical Design flow including floorplanning, placement, CTS, routing, and extraction * Strong scripting skills in Tcl, Python, Perl, or Shell for automation and flow development Good to Have * Experience with advanced technology nodes such as 7nm, 5nm, 3nm, or below * Exposure to package-aware analysis, thermal analysis, and low-power methodologies * Experience in leading signoff closure for large-scale SoC or high-performance compute designs Success in This Role Looks Like * Achieving robust IR/EM signoff with minimal iterations and successful tapeout execution * Early identification and resolution of power integrity risks impacting performance and reliability * Improved signoff productivity through methodology enhancements and automation initiatives * Strong technical leadership and collaboration across implementation and signoff teams Location On-site – Bengaluru Applicants: Qualcomm is an equal opportunity...